1. Field of the Invention
The invention relates to a signal converting element, and in particular to a synchronization element for converting an asynchronous pulse signal into a synchronous pulse signal with reference to a clock signal.
2. Description of the Related Art
In line with the great progress in semiconductor technology, digital circuits are getting increasingly complicated. In order to enhance operating speed and efficiency of a current widely-used personal computer, sub-systems within a computer system can use different operating frequencies. For example, the external operating frequency of a CPU is approximately 66 MHz or 100 MHz while the operating frequency of the PCI is approximately 33 MHz or 66 MHz and the operating frequency of a network interface electrically connected to the PCI is around 10 MHz or 100 MHz. In this multi-operating frequency system, a queue operation is always used to transmit data for increasing its own efficiency. In a queue operation, it is necessary to convert an asynchronous control signal into a control signal which is synchronous to a reference clock signal thereof Moreover, the sub-systems with different operating frequencies require this kind of signal conversion for normal operations.
FIG. 1 is a block circuit diagram showing a system simultaneously having two operating frequencies. As shown in FIG. 1, data transmission between a mainframe 120 and a peripheral device 110 is implemented by using two queue devices 130 and 145. The mainframe 120 operates with a clock signal CK1 while the peripheral device 110 operates with a clock signal CK2. Data can be transmitted from the peripheral device 110 and stored in a queue 135 of the queue device 130 through a signal line DIN in coordination with a control signal PUSH. The mainframe 120 reads the data from the queue 135 through a signal line DOUT in coordination with a control signal POP. Inversely, data can also be transmitted from the mainframe and stored in a queue 145 of the queue device 140 through a signal line DIN' in coordination with a control signal PUSH'. Similarly, the peripheral device 110 reads the data from the queue 145 through a signal line DOUT' in coordination with a control signal POP'.
Since the mainframe 120 and the peripheral device 110 operate with different reference clock signals CK1 and CK2, an asynchronous pulse signal transmitted from the mainframe 120 or the peripheral device 110 must be converted into a synchronous pulse signal with reference to an internal operating clock by the queue device 130 or the 140 for normal operation.
In the prior art, the state machine of Gray code is commonly used to convert different frequencies of clock signals into the same frequency of clock signals. With a simple principle, a signal is changed only toward one direction by allowing only one bit to be changed. However, using the state machine of Gray code to achieve signal synchronization can only convert a lower frequency clock signal into a higher frequency clock signal. That is, an original input signal (clock signal) must has a larger width than a new reference clock signal. In other words, the prior method cannot be used to convert a higher clock signal into a lower clock signal.